Our lab rethinks computer architecture for emerging workloads that are memory-bound, stateful, and irregular, where conventional throughput-driven designs fall short. We develop predictable, efficient, and verifiable computing systems through rigorous microarchitectural design and hardware-software co-design. The lab is led by Prof. Aruna Jayasena (@ArchFx) and our work spans across AI hardware for large language model inference, acceleration of secure computation such as fully homomorphic encryption, and reconfigurable system software for managing heterogeneous accelerators, aiming to build high-performance platforms with strong guarantees of correctness, efficiency, and resilience.
Updates
- Apr 7, 2026 Aruna will serve as Session Chair for 'Microarchitectural & Cache Side-Channels (Regular Session 7)' at IEEE HOST 2026, taking place on May 6 at the International Ballroom A, Hilton McLean Tysons Corner, VA. Read more...
- Mar 26, 2026 Aruna received the prestigious EDAA Outstanding Dissertation Award in 'New Directions in Safety, Reliability, and Security-Aware Hardware Design, Validation, and Test'. Each year, the European Design Automation Association selects only four dissertations worldwide, and his dissertation was recognized in this category for 2026. Read more...
- Aug 18, 2025 Aruna joined the University of Tennessee at Chattanooga as an Tenure-Track Assistant Professor in Fall 2025. With this we officially launched the ARCH Lab for Computer Architecture and Systems.