Dakshina Tharindu, Aruna Jayasena and Prabhat Mishra, “A Tutorial on Secure and Efficient Firmware Delivery”, IEEE Design & Test (DnT), 2026.
Yuntao Liu, Aruna Jayasena, Prabhat Mishra and Ankur Srivastava, “TroLL: Exploiting Structural Similarities Between Logic Locking and Hardware Trojans”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2025.
Aruna Jayasena, Sai Suprabhanu Nallapaneni and Prabhat Mishra, “FuSS: Coverage-Directed Hardware Fuzzing with Selective Symbolic Execution”, ACM Transactions on Embedded Computing Systems (TECS), 2025.
Aruna Jayasena and Prabhat Mishra, “FirmWall: Directed Symbolic Execution of Firmware Binaries for Defending against Unauthorized System Calls”, IEEE Transactions on Information Forensics & Security (TIFS), 2025.
Hansika Weerasena, Aruna Jayasena, Christina Boucher and Prabhat Mishra, “Formal Verification of Bioinformatics Software using Model Checking and Theorem Proving”, Briefings in Bioinformatics (BIB), 2025.
Aruna Jayasena, Richard Bachmann and Prabhat Mishra, “CISELeaks: Information Leakage Assessment of Cryptographic Instruction Set Extension Prototypes”, IEEE Transactions on Information Forensics & Security (TIFS), 2025.
Sahan Nelundeniyalage, Aruna Jayasena and Prabhat Mishra, “Information Leakage through Physical Layer Supply Voltage Coupling Vulnerability”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2025.
Aruna Jayasena and Prabhat Mishra, “HIVE: Scalable Hardware-Firmware Co-Verification using Scenario-based Decomposition and Automated Hint Extraction”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2024.
Hasini Witharana, Aruna Jayasena and Prabhat Mishra, “Sequence-Based Incremental Concolic Testing of RTL Models”, ACM Transactions on Design Automation of Electronic Systems (TODAES), 2024.
Aruna Jayasena and Prabhat Mishra, “Directed Test Generation for Hardware Validation: A Survey”, ACM Computing Surveys (CSUR), 2024.
Aruna Jayasena, Emma Andrews and Prabhat Mishra, “TVLA*: Test Vector Leakage Assessment on Hardware Implementations of Asymmetric Cryptography Algorithms”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2023.
Aruna Jayasena and Prabhat Mishra, “Scalable Detection of Hardware Trojans using ATPG-based Activation of Rare Events”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2023.
Aruna Jayasena, Binod Kumar, Subodha Charles, Hasini Witharana and Prabhat Mishra, “Network-on-Chip Trust Validation using Security Assertions”, Journal of Hardware and Systems Security (HASS), 2022.
Hasini Witharana, Aruna Jayasena, Andrew Whigham and Prabhat Mishra, “Automated Generation of Security Assertions for RTL Models”, Journal on Emerging Technologies in Computing Systems (JETC), 2022.
Aruna Jayasena, “Register Transfer Level Disparity Generator with Stereo Vision”, Journal of Open Research Software (JORS), 2021.
Conference
Emma Andrews, Aruna Jayasena and Prabhat Mishra, “Semantic-Guided Test Generation using Fine-Tuned LLMs for Validation of Hardware Accelerators”, The 27th International Symposium on Quality Electronic Design (ISQED), 2026.
Aruna Jayasena, Sai Suprabhanu Nallapaneni and Prabhat Mishra, “FuSS: Coverage-Directed Hardware Fuzzing with Selective Symbolic Execution”, ACM/IEEE International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), 2025.
Aruna Jayasena, Richard Bachmann and Prabhat Mishra, “EvilCS: An Evaluation of Information Leakage through Context Switching on Security Enclaves”, Design Automation and Test in Europe (DATE), 2024.
Aruna Jayasena and Prabhat Mishra, “Design for Trust utilizing Rareness Reduction”, International Conference on VLSI Design (VLSID), 2024.
Aruna Jayasena and Prabhat Mishra, “Towards Formal Verification of Hardware-Firmware Implementations”, Semiconductor Research Corporation (SRC-TECHCON), 2023.
Aruna Jayasena, Khushboo Rani and Prabhat Mishra, “Efficient Finite State Machine Encoding for Defending Against Laser Fault Injection Attacks”, 40th IEEE International Conference on Computer Design (ICCD), 2022.
Aruna Jayasena and Prabhat Mishra, “Assertion-based Security Validation of Network-on-Chip Architectures”, Semiconductor Research Corporation (SRC-TECHCON), 2022.
Hasini Witharana, Aruna Jayasena and Prabhat Mishra, “Automated Generation of Security Assertions for RTL Models”, Semiconductor Research Corporation (SRC-TECHCON), 2021.
Book Chapters
Aruna Jayasena, Emma Andrews and Prabhat Mishra, “Quantum Testing and Validation”, Design Automation for Quantum Computing, Springer, 2025.
Aruna Jayasena, Subodha Charles and Prabhat Mishra, “Network-on-Chip Security and Trust Verification”, Network-on-Chip Security and Privacy, Springer, 2021.
Patents
Prabhat Mishra, Aruna Jayasena and Sai Suprabhanu Nallapaneni, “System and Method for Hardware Fuzzing with Selective Symbolic Execution”, U.S. Provisional Patent Application No. 63/866,026, filed August 18, 2025, 2025. (Pending)
Prabhat Mishra, Sahan Sanjaya and Aruna Jayasena, “System and Method for Side-Channel Analysis using Context Switch Induced Power Signature”, U.S. Provisional Patent Application No. 63/844,942, filed July 16, 2025, 2025. (Pending)
Prabhat Mishra, Aruna Jayasena, “Scalable Detection of Hardware Trojans using ATPG-based Activation of Rare Events”, U.S. Provisional Patent Application No. 63/582,388, filed September 13, 2023, 2023. (Pending)
Prabhat Mishra, Aruna Jayasena and Emma Andrews, “Test Vector Leakage Assessment of Asymmetric Cryptography Algorithms”, U.S. Provisional Patent Application No. 63/467,784, filed May 19, 2023, 2023. (Pending)
S. Sooriyaarachchi, C. Gamage, C. de Silva, S. Pallemulla, S. Dharmaratna, S. Ranathunga, A. Jayasena, K. Ratnayake and S. Kahawala, “Computer Vision Based Multi-spectral Automatic Fabric Quality Inspection Machine with Physical Color Referencing”, National ID LK/P/13468, April 09, 2021, 2021. (Pending)
S. Sooriyaarachchi, C. Gamage, C. de Silva, S. Pallemulla, S. Dharmaratna, S. Ranathunga, A. Jayasena, K. Ratnayake and S. Kahawala, “Method and Apparatus for Detecting Surface Defects”, PCT International Application PCT/IB2021/052945, April 09, 2021, 2021. (Ceased (2023))
S. Sooriyaarachchi, C. Gamage, C. de Silva, S. Pallemulla, S. Dharmaratna, S. Ranathunga, A. Jayasena, K. Ratnayake and S. Kahawala, “Method and Apparatus for Detecting Surface Defects”, National Patent LK/P/21709, April 08, 2021, 2021. (Granted)