Stateful Sequential Dataflow AI Hardware

Stateful AI workloads such as autoregressive generation, sequence modeling, and streaming inference place unique pressure on conventional accelerator designs. At ARCH Lab, we study dataflow-driven architectures that better exploit temporal locality, predictable execution, and state reuse across long-running computations.

Our work investigates accelerator organizations that reduce data movement, improve memory efficiency, and provide scalable support for sequential and stateful computation. By combining architectural specialization with hardware-software co-design, we aim to build AI systems that are both efficient and structurally well suited for next-generation intelligent applications.

Research themes

• Stateful and sequential AI execution models
• Memory-centric accelerator design
• Dataflow scheduling for long-context inference
• Efficient support for structured and irregular workloads
• Hardware-software co-design for emerging AI systems